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Machine language of Nabaztag Structures A
Page 1
Machine language of Nabaztag
Structure A
December 2005
Page 2
1 INTRODUCTION ................................................................................................... 5
2 GENERAL INFORMATION ..................................................................................................... 5
3 STRATEGY .......................................................................................................... 5
4 VIRTUAL MACHINE ......................................................................................... 5
4.1 States ............................................................................................................................. 5
4.2 Regular operation ............................................................................................. 6
4.3 Crush system .................................................................................................................. 6
4.4 Interruptions ................................................................................................................ 7
4.5 Sending of data towards the waiter ................................................................................ 7
4.6 Unknown instruction ................................................................................................... 7
4.7 Registers of state ............................................................................................................ 7
4.8 Modes of addressing ...................................................................................................... 8
4.8.1 - (inherent) 0 byte .............................................................................................. 8
4.8.2 I .......................................................................................................................... 8
4.8.3 R .......................................................................................................................... 8
4.8.4 R, I ....................................................................................................................... 8
4.8.5 R, R' ..................................................................................................................... 8
4.8.6 I, I' ...................................................................................................................... 8
4.8.7 R, I, R' .................................................................................................................. 8
4.8.8 W ........................................................................................................................ 8
4.8.9 R, W ...................................................................................................................... 8
4.8.10 R, R, W .................................................................................................................. 8
4.9 Instruction set ........................................................................................................ 8
4.9.1 LD_ri (0x0) ......................................................................................................... 9
4.9.2 ADD_ri (0x10) ................................................................................................... 9
4.9.3 SUB_ri (0x20) .................................................................................................... 9
4.9.4 AND_ri (0x30) ................................................................................................... 9
4.9.5 OR_ri (0x40) ...................................................................................................... 9
4.9.6 LDR_ri (0x50) .................................................................................................... 9
4.9.7 STR_ri (0x60) ..................................................................................................... 9
4.9.8 NOP_o (0x70) .................................................................................................... 9
4.9.9 RTI_o (0x72) ...................................................................................................... 9
4.9.10 CLRCC_o (0x73) .............................................................................................. 9
4.9.11 SETCC_o (0x74) .............................................................................................. 9
4.9.12 ADDCC_rr (0x75) ............................................................................................ 9
4.9.13 SUBCC_rr (0x76) ........................................................................................... 10
Page 3
4.9.14 INCW_rr (0x77) ............................................................................................. 10
4.9.15 DECW_rr (0x78) ............................................................................................ 10
4.9.16 MULW_rr (0x79) ........................................................................................... 10
4.9.17 INPUTRST_r (0x7a) ....................................................................................... 10
4.9.18 INT_r (0x7b) .................................................................................................. 10
4.9.19 WAIT_r (0x7d) ............................................................................................... 10
4.9.20 WAIT_i (0x7e) ............................................................................................... 10
4.9.21 RND_r (0x7f) ................................................................................................. 10
4.9.22 DEC_r (0x80) ................................................................................................. 10
4.9.23 INC_r (0x81) .................................................................................................. 10
4.9.24 CLR_r (0x82) ................................................................................................. 10
4.9.25 NEG_r (0x83) ................................................................................................. 11
4.9.26 NOT_r (0x84) ................................................................................................. 11
4.9.27 TST_r (0x85) .................................................................................................. 11
4.9.28 LD_rr (0x86) .................................................................................................. 11
4.9.29 ADD_rr (0x87) ............................................................................................... 11
4.9.30 SUB_rr (0x88) ................................................................................................ 11
4.9.31 MUL_rr (0x89) ............................................................................................... 11
4.9.32 AND_rr (0x8a) ............................................................................................... 11
4.9.33 OR_rr (0x8b) .................................................................................................. 11
4.9.34 EOR_rr (0x8c) ................................................................................................ 11
4.9.35 LSL_rr (0x8d) ................................................................................................. 11
4.9.36 LSR_rr (0x8e) ................................................................................................. 11
4.9.37 ASR_rr (0x8f) ................................................................................................. 12
4.9.38 ROL_rr (0x90) ................................................................................................ 12
4.9.39 ROR_rr (0x91) ................................................................................................ 12
4.9.40 CMP_rr (0x92) ............................................................................................... 12
4.9.41 BIT_rr (0x93) ................................................................................................. 12
4.9.42 LDR_rr (0x94) ................................................................................................ 12
4.9.43 LDR_rir (0x95) ............................................................................................... 12
4.9.44 STR_rr (0x96) ................................................................................................. 12
4.9.45 STR_rir (0x97) ............................................................................................... 12
4.9.46 LDT_rrw (0x98) ............................................................................................. 12
4.9.47 LDTW_rw (0x99) ........................................................................................... 12
4.9.48 INPUT_rw (0x9a) ........................................................................................... 13
4.9.49 RTIJ_w (0x9b) ................................................................................................ 13
4.9.50 BRA_w (0x9c) ................................................................................................ 13
4.9.51 BEQ_w (0x9d) ................................................................................................ 13
4.9.52 BNE_w (0x9e) ................................................................................................ 13
4.9.53 BGT_w (0x9f) ................................................................................................ 13
4.9.54 BGE_w (0xa0) ................................................................................................ 13
4.9.55 BLT_w (0xa1) ................................................................................................ 13
4.9.56 BLE_w (0xa2) ................................................................................................ 13
4.9.57 BHI_w (0xa3) ................................................................................................. 13
4.9.58 BHS_w (0xa4) ................................................................................................ 13
4.9.59 BLO_w (0xa5) ................................................................................................ 13
4.9.60 BLS_w (0xa6) ................................................................................................. 13
4.9.61 LED_rr (0xa7) ................................................................................................ 13
4.9.62 PALETTE_rr (0xa8) ....................................................................................... 13
4.9.63 PUSH_ii (0xaa) ............................................................................................... 14
Page 4
4.9.64 PULL_ii (0xab) ............................................................................................... 14
4.9.65 BSR_w (0xac) ................................................................................................. 14
4.9.66 RTS_o (0xad) ................................................................................................. 14
4.9.67 MOTOR_rr (0xae) .......................................................................................... 14
4.9.68 MIDIPLAY_r (0xaf) ....................................................................................... 14
4.9.69 MIDISTOP_o (0xb0) ...................................................................................... 14
4.9.70 WAVPLAY_r (0xb1) ...................................................................................... 14
4.9.71 WAVSTOP_o (0xb2) ...................................................................................... 14
4.9.72 MSEC_rr (0xb3) ............................................................................................. 14
4.9.73 SEC_rr (0xb4) ................................................................................................. 14
4.9.74 BUT3_r (0xb5) ............................................................................................... 14
4.9.75 VOL_r (0xb6) ................................................................................................. 15
4.9.76 MVOL_r (0xb7) .............................................................................................. 15
4.9.77 PUSHBUTTON_r (0xb8) ............................................................................... 15
4.9.78 SRC_rr (0xb9) ................................................................................................ 15
4.9.79 BRAT_rw (0xba) ............................................................................................ 15
4.9.80 BSRT_rw (0xbb) ............................................................................................ 15
4.9.81 OSC_rr (0xbc) ................................................................................................ 15
4.9.82 INV_rr (0xbd) ................................................................................................. 15
4.9.83 DIV_rr (0xbe) ................................................................................................. 15
4.9.84 HSV_o (0xbf) ................................................................................................. 15
4.9.85 MOTORGET_rr (0xc0) .................................................................................. 15
4.9.86 MUSIC_r (0xc1) ............................................................................................. 15
4.9.87 DOWNLOAD_r (0xc2) .................................................................................. 16
4.9.88 SEND_rr (0xc4) .............................................................................................. 16
4.9.89 SENDREADY_r (0xc5) .................................................................................. 16
4.9.90 LASTPING_rr (0xc6) ..................................................................................... 16
5 FORMAT OF THE SCREENS ..................................................................................... 16
5.1 Structure of the response of the waiter ........................................................................... 16
5.2 Structure of the modifications of the sources ................................................................... 16
5.3 Structure of the screens of bytecode ............................................................................. 16
Page 5
1
Introduction
This document describes the machine language of the virtual machine integrated in the object:
Nabaztag.
The information given in this document is not contractual and no support is
given concerning this information or of possible applications which would use them.
2
General
For reasons of technology of connection, and cost of exploitation, there is not
streaming between the platform and the object. The platform regularly transmits data to
the object, on request of this last.
One is interested in this document in the format of the data transmitted by the platform to
the object, and in particular with the machine language of the virtual machine.
3
Strategy
One fixes oneself like objective of:
- to limit the treatment carried out by the object: the received data must be very close
demonstrations to be produced
- to keep a great flexibility, not to lock up the object in behaviors
similar
- to allow a continuity of operation of the object in the event of loss of connection,
during at least a few minutes
So the adopted solution consists in defining an architecture of the type `virtual machine'
with an instruction set reduced and adapted to the problem. The transmitted data will be
simply the `machine language' used by the object. They will be called “the program” of
the object.
When the object receives a program different from the precedent, the question of the transition is
regulated according to the state of the object and the indications provided by the new program. It
is to be noted that the platform has obviously the knowledge of the successive programs
transmitted to the object (since it is it which produces them), and it is thus with it that returns work
to regulate these transitions.
4
Virtual machine
4.1 States
The virtual machine contains the following elements:
- a memory programs, which contains the program received since the platform.
maximum size is of 64ko (16 bits).
- a RAM of 256 bytes, dedicated to the machine virtual, and used also like
crush system
- a RAM of “sources” of 64 bytes, in read-only for the virtual machine and in
Write-only for the waiter
Page 6
- a meter of program 16 bits, which points towards the instruction to carry out: PC
- a meter of waiting: W
- 16 accumulators 8 bits: R0, R1,…, R15
- DC: a bit of selected
- cmp1, cmp2: two registers of state
- for each interruption (there can be 16 of them)
O a pointer programs “input” which indicates the code to be carried out in case
of interruption (- 1 if the interruption must be ignored): input.0,…, input.15
The initial values are:
- PC: 17
- W: 0
- R0,… R15: 0
- For the interruptions:
O Input.i=-1
4.2 Regular operation
The operation of the virtual machine is the same one with each step. These steps take place
regularly, approximately 20 times a second.
- W is examined:
O if W<>0, one décrémente W
O if not, one reads the next instruction of the program, and one interprets it
one starts again so as to read with more the 1.000.000 instructions, so much
that W=0
The object functions in sequential loop, and also carried out between each step of
operations of management of the communications network, the audio readings, the leds,…
The limit with 1.000.000 of instructions by step is thus a safety, which ensures that the machine
virtual the hand for the other treatments returns, but it should never be reached:
program in machine language must itself regularly indicate that it arrived at the end
step, by positioning the value W at least to 1 (see functions WAIT).
4.3 Crush system
The pile system is used for:
- to store the value of the meter programs at the time of the call of a subroutine
- to store the value of the meter programs, the registers of state and reserve at the time
of an interruption
- to store temporarily various registers (functions SWEATER and PUSH)
The pile system is stored in the RAM of the virtual machine. The pointer of pile system
is the R15 register.
Stacking consists with:
- décrémenter R15
- to store the value to be piled up in the RAM, with the R15 address
Dépilement consists with:
- to read the value to be depilated in the RAM, with the R15 address
- to increment R15
Page 7
4.4 Interruptions
When, between two steps, the virtual machine detects an event leading to
the execution of an interruption (for example the interruption `I'), operation is it
according to:
- If input.i = -1, nothing to make
- If not, to pile up PC, DC, CMP1, CMP2, then to position PC on the value input.i
For Nabaztag, the interruptions are as follows:
- 0: support on the pushbutton
- 1: relaxation of the pushbutton
- 2: change of position of the button 3 states
- 14: exception (opcode unknown)
- 15: timer (all 20 steps)
The other interruptions are usable by the program as interruptions software.
4.5 Sending of data towards the waiter
The virtual machine can transmit data to the platform. These data are
words of 16 bits. Operation is as follows:
- the virtual machine sends a message 16 bits: the buffer of emission is regulated on
“full”
- the network layer will transmit the message, then to regulate the buffer of emission on
“vacuum”
- the virtual machine should wait until the buffer is empty before re-emitting one
message.
4.6 Unknown instruction
When the virtual machine falls on unknown Opcode, it calls the interruption 14,
then a Reset software carries out.
4.7 Registers of state
The mechanism of register of state of the virtual machine is simplified compared to the microphone
traditional processors.
It is composed of three registers of state:
- DC: bit of reserve
- CMP1: operator 1 (8 bits) of the last operation
- CMP2: operator 2 (8 bits) of the last operation
For all the operations:
- CMP1 is in charge with the result of the operation
- CMP2 is charged with 0
There is an exception: the operation CMP, which charges CMP1 and CMP2 with the two operands.
If the result of the operation is on 16 bits, CMP1 is regulated with the result of OR
logic on the byte of strong weight and the weak byte of weight. This does not allow whereas the tests
BEQ and BNE.
Page 8
4.8 Modes of addressing
The instructions have the following structure:
- an operator, who contains in particular the mode of addressing
- zero, one or more bytes of operands
4.8.1 - (inherent) 0 byte
No argument: for example RTI
4.8.2 I
An entirety 8 bits. The entirety is stored in the byte of the operand.
4.8.3 R
A register. The register is stored in the 4 bits of weak weight of the operand.
4.8.4 R, I
A register and an entirety. This mode is used in a special way with fusion of the opcode and
register: the opcode uses only the 4 bits of strong weight; one uses the 4 bits of weak weight
to store the register. Then one uses a byte of operand for the entirety.
4.8.5 R, R'
Two registers. The first uses the 4 bits of strong weight of the operand; the second uses some
4 bits of weak weight.
4.8.6 I, I'
Two entireties. The first is in the first byte of the operand, the second in
second byte.
4.8.7 R, I, R'
Two registers and an entirety. The first byte of the operand gathers the two registers, it
second contains the entirety
4.8.8 W
An address 16 bits, stored in the BigEndian order.
4.8.9 R, W
A register and an address 16 bits. The register is stored in the 4 bits of weak weight of
first byte of the operand, the address in the two following.
4.8.10 R, R, W
Two registers and an address 16 bits. The first byte of the operand gathers both
registers, the two following contain the address.
4.9 Instruction set
One finds hereafter the instruction set of the virtual machine. The form is:
- mnémonique_adressage (0xopcode).
Page 9
In the case of addressing “R, I”, the real opcode is obtained by adding the number with
register with the basic opcode.
For example, ADD r2, $47 result in two bytes: $12, $47
4.9.1 LD_ri (0x0)
Charge the register with the value of the entirety
Modify CMP1, CMP2.
4.9.2 ADD_ri (0x10)
Add to the register the value of the entirety
Modify CMP1, CMP2.
4.9.3 SUB_ri (0x20)
Withdrawn register the value of the entirety
Modify CMP1, CMP2.
4.9.4 AND_ri (0x30)
Carry out one AND logic between the register and the entirety, and stores the result in the register.
Modify CMP1, CMP2.
4.9.5 OR_ri (0x40)
Carry out one OR logic between the register and the entirety, and stores the result in the register.
Modify CMP1, CMP2.
4.9.6 LDR_ri (0x50)
Charge the register with the i-ème byte of the RAM (where I is the entirety passed in parameter).
Modify CMP1, CMP2.
4.9.7 STR_ri (0x60)
Store the register in the i-ème byte of the RAM (where I is the entirety passed in parameter)
4.9.8 NOP_o (0x70)
Does not do anything
4.9.9 RTI_o (0x72)
End of interruption: depilate PC, DC, CMP1, CMP2
4.9.10 CLRCC_o (0x73)
To zero bit DC gives
4.9.11 SETCC_o (0x74)
At 1 bit DC puts
4.9.12 ADDCC_rr (0x75)
Carry out the addition of two registers and reserve and puts the result in the first register.
Modify CMP1, CMP2.
Page 10
4.9.13 SUBCC_rr (0x76)
Carry out the subtraction of two registers and reserve and puts the result in the first
register.
Modify CMP1, CMP2.
4.9.14 INCW_rr (0x77)
Carry out an incrementing on a meter 16 bits which would be consisted of the first register
for the strong weight, and of the second for the weak weight.
Modify CMP1, CMP2.
4.9.15 DECW_rr (0x78)
Carry out a decrementation on a meter 16 bits which would be consisted of the first register
for the strong weight, and of the second for the weak weight.
Modify CMP1, CMP2.
4.9.16 MULW_rr (0x79)
Carry out the not signed multiplication of two registers, and stores the strong weight of the result in
the first, and the weak weight in the second.
Modify CMP1, CMP2.
4.9.17 INPUTRST_r (0x7a)
Re-initialized the interruption whose number is contained in the register.
4.9.18 INT_r (0x7b)
Cause an interruption software whose number is contained in the register.
4.9.19 WAIT_r (0x7d)
Régle the value W of the virtual machine with the value of the register.
4.9.20 WAIT_i (0x7e)
Régle the value W of the virtual machine with the value of the entirety.
4.9.21 RND_r (0x7f)
Turn over in the register a random value on 8 bits.
Modify CMP1, CMP2.
4.9.22 DEC_r (0x80)
Décrémente the register.
Modify CMP1, CMP2.
4.9.23 INC_r (0x81)
Increment the register.
Modify CMP1, CMP2.
4.9.24 CLR_r (0x82)
Regulate the register with value 0.
Modify CMP1, CMP2.
Page 11
4.9.25 NEG_r (0x83)
Opposite the sign of the register.
Modify CMP1, CMP2.
4.9.26 NOT_r (0x84)
Carry out a transformation of the register: bits 0 become bits 1 and conversely.
Modify CMP1, CMP2.
4.9.27 TST_r (0x85)
Test the value of a register.
Modify CMP1, CMP2.
4.9.28 LD_rr (0x86)
Charge the first register with the value of the second.
Modify CMP1, CMP2.
4.9.29 ADD_rr (0x87)
Add to the first register the value of the second.
Modify CMP1, CMP2.
4.9.30 SUB_rr (0x88)
Withdrawn first register the value of the second.
Modify CMP1, CMP2.
4.9.31 MUL_rr (0x89)
Multiply two registers and stores the result in the first.
Modify CMP1, CMP2.
4.9.32 AND_rr (0x8a)
Carry out one AND logic between two registers and stores the result in the first.
Modify CMP1, CMP2.
4.9.33 OR_rr (0x8b)
Carry out one OR logic between two registers and stores the result in the first.
Modify CMP1, CMP2.
4.9.34 EOR_rr (0x8c)
Carry out one OR EXCLUSIVE logic between two registers and stores the result in the first.
Modify CMP1, CMP2.
4.9.35 LSL_rr (0x8d)
Carry out a shift on the left on the first register. The number of bits of shift is
defined by the value of the second.
Modify CMP1, CMP2.
4.9.36 LSR_rr (0x8e)
Carry out a logic shift on the right on the first register. The number of bits of shift
is defined by the value of the second.
Modify CMP1, CMP2.
Page 12
4.9.37 ASR_rr (0x8f)
Carry out an arithmetic shift on the right on the first register. The number of bits of
shift is defined by the value of the second.
Modify CMP1, CMP2.
4.9.38 ROL_rr (0x90)
Carry out a rotation on the left on the first register. The number of bits of shift is
defined by the value of the second.
Modify CMP1, CMP2.
4.9.39 ROR_rr (0x91)
Carry out a rotation on the right on the first register. The number of bits of shift is defined
by the value of the second.
Modify CMP1, CMP2.
4.9.40 CMP_rr (0x92)
Compare two registers. Charge CMP1 with the first, and CMP2 with the second.
4.9.41 BIT_rr (0x93)
Carry out one AND logic between two registers, but without storing the result.
Modify CMP1, CMP2.
4.9.42 LDR_rr (0x94)
Charge the first register with the i-ème byte of the RAM (where I is the value of the second register)
Modify CMP1, CMP2.
4.9.43 LDR_rir (0x95)
Charge the first register with the i-ème byte of the RAM (where I is the sum of the entirety and of
value of the second register)
Modify CMP1, CMP2.
4.9.44 STR_rr (0x96)
Store the first register in the i-ème byte of the RAM (where I is the value of the second register)
4.9.45 STR_rir (0x97)
Store the first register in the i-ème byte of the RAM (where I is the sum of the entirety and of
value of the second register)
4.9.46 LDT_rrw (0x98)
Charge in the first register the i-ème value of a table (where I is the value of the second
register). The address of the beginning of the table passed in parameter.
Modify CMP1, CMP2.
4.9.47 LDTW_rw (0x99)
Charge in the first register the i-ème value of a table (where I is the value 16 bits
constituted by the registers R3 (strong weight) and R4 (weak weight)). The address of the beginning of the table
passed in parameter.
Modify CMP1, CMP2.
Page 13
4.9.48 INPUT_rw (0x9a)
Regulate the address of an interruption. The number of the interruption is the value of the register.
4.9.49 RTIJ_w (0x9b)
End of interruption, with jump: depilate PC, DC, CMP1, CMP2, then rule PC with the address
passed in parameter.
4.9.50 BRA_w (0x9c)
Regulate PC with the address passed in parameter (unconditional jump).
4.9.51 BEQ_w (0x9d)
Regulate PC with the address passed in parameter, if Cmp1=Cmp2
4.9.52 BNE_w (0x9e)
Regulate PC with the address passed in parameter, if Cmp1<>Cmp2
4.9.53 BGT_w (0x9f)
Regulate PC with the address passed in parameter, if Cmp1>Cmp2 (signed)
4.9.54 BGE_w (0xa0)
Regulate PC with the address passed in parameter, if Cmp1>=Cmp2 (signed)
4.9.55 BLT_w (0xa1)
Regulate PC with the address passed in parameter, if Cmp1<Cmp2 (signed)
4.9.56 BLE_w (0xa2)
Regulate PC with the address passed in parameter, if Cmp1<=Cmp2 (signed)
4.9.57 BHI_w (0xa3)
Regulate PC with the address passed in parameter, if Cmp1>Cmp2 (not signed)
4.9.58 BHS_w (0xa4)
Regulate PC with the address passed in parameter, if Cmp1>=Cmp2 (not signed)
4.9.59 BLO_w (0xa5)
Regulate PC with the address passed in parameter, if Cmp1<Cmp2 (not signed)
4.9.60 BLS_w (0xa6)
Regulate PC with the address passed in parameter, if Cmp1<=Cmp2 (not signed)
4.9.61 LED_rr (0xa7)
Modify a led. The first register contains the number of the led, the second the time of
transition (counted in step). The new color of the led is in the registers R0, R1, R2.
4.9.62 PALETTE_rr (0xa8)
Regulate the register R0, R1 and R2 with a color. The first register defines the color (0:
black, 1: red, 2: green, 3: yellow, 4: blue, 5: purple, 6: cyan, 7: white,…) and the second defines
the intensity (0: black,…, 255: very clearly).
Page 14
4.9.63 PUSH_ii (0xaa)
Safeguard registers in the pile system. The two entireties define 16 bits. Each bit
corresponds to a register to safeguard (R0,…, R14, DC).
For the first operand: DC, R14, R13,…, R8 (in the order bit7 towards bit0).
For the second operand: R7, R6,…, R0 (in the order bit7 towards bit0).
4.9.64 PULL_ii (0xab)
Recover registers since the pile system. The two entireties define 16 bits. Each
bit corresponds to a register to recover (R0,…, R14, DC).
For the first operand: DC, R14, R13,…, R8 (in the order bit7 towards bit0).
For the second operand: R7, R6,…, R0 (in the order bit7 towards bit0).
4.9.65 BSR_w (0xac)
Carry out a nonconditional jump towards the address passed in parameter, and safeguards the PC
running (call to a subroutine) in the pile system.
4.9.66 RTS_o (0xad)
End of subroutine: depilate value PC of the pile system
4.9.67 MOTOR_rr (0xae)
Order the engines: the first register indicates the number of the engine (0 or 1), the second
indicate the direction (0, 1 or 2; 0 mean the stop)
4.9.68 MIDIPLAY_r (0xaf)
Launch the player midday on an audio file. The register contains the number of the audio file in
tables of the audio files.
4.9.69 MIDISTOP_o (0xb0)
Stop the player midday.
4.9.70 WAVPLAY_r (0xb1)
Launch the player adpcm on an audio file. The register contains the number of the audio file
in the tables of the audio files.
4.9.71 WAVSTOP_o (0xb2)
Stop the player adpcm.
4.9.72 MSEC_rr (0xb3)
Turn over in a value 16 bits corresponding to a time in milliseconds. The first
register will contain the byte of strong weight, the second the weak byte of weight.
4.9.73 SEC_rr (0xb4)
Turn over in a value 16 bits corresponding to a time in seconds. The first register
will contain the byte of strong weight, the second the weak byte of weight.
4.9.74 BUT3_r (0xb5)
Charge the register with the position of the button 3 states (0, 1 or 2)
Page 15
4.9.75 VOL_r (0xb6)
Regulate applicatif volume with the value of the register.
4.9.76 MVOL_r (0xb7)
Regulate the master volume with the value of the register. Real volume is the product of volume
applicatif and of the master volume.
4.9.77 PUSHBUTTON_r (0xb8)
Charge the register with the position of the pushbutton (0 or 1)
4.9.78 SRC_rr (0xb9)
Charge the first register with the value of the i-ème source (where I is the value of the second
register).
Modify CMP1, CMP2.
4.9.79 BRAT_rw (0xba)
Carry out an unconditional jump. The new value of the PC is required in the table
addresses. The register contains the index in this table.
4.9.80 BSRT_rw (0xbb)
Carry out an unconditional jump. The new value of the PC is required in the table
addresses. The register contains the index in this table. The PC running is safeguarded in
crush system (call to a subroutine)
4.9.81 OSC_rr (0xbc)
Charge the first register with the value 128* (1-cos i*pi/128), or I is the value of the second
register.
Modify CMP1, CMP2.
4.9.82 INV_rr (0xbd)
Carry out calculation 65536/r (where R is the second register), and writes the strong weight of the result in
first register, and the weak weight in the second.
4.9.83 DIV_rr (0xbe)
Carry out division 256*r1/r2, and writes the strong weight of the result in the first register, and it
weak weight in the second.
4.9.84 HSV_o (0xbf)
Carry out a conversion HSV - > RGB to the registers R0, R1, R2.
4.9.85 MOTORGET_rr (0xc0)
Charge the first register with the meter associated with the engine whose number passed in
the second register.
4.9.86 MUSIC_r (0xc1)
Charge the register with the state of the players (0: no audio reading in progress, 1: reading midday in
run, 2: reading adpcm in progress).
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4.9.87 DOWNLOAD_r (0xc2)
Charge the register with the state of the automat network (bit 1: remote loading in progress, bit 2:
request network in progress).
Modify CMP1, CMP2.
4.9.88 SEND_rr (0xc4)
Ask for the sending of a value 16 bits the waiter; the first register contains the strong weight, it
second contains the weak weight.
4.9.89 SENDREADY_r (0xc5)
Charge the register with the state of the automat of sending (1: loan to be emitted).
Modify CMP1, CMP2.
4.9.90 LASTPING_rr (0xc6)
Turn over the value 16 bits of the time passed, in seconds, since last successful connection
towards the waiter. The first register contains the strong weight, the second contains the weak weight.
Modify CMP1, CMP2.
5
Format of the screens
5.1 Structure of the response of the waiter
The answer consists of a variable number of operations.
Each operation with the following structure:
- a code operation
- size of the arguments of the operation, on 24 bits
- then arguments in question
The code $ff means the end of the answer, it is not followed size.
The principal codes are:
$04
modification of the sources of a screen of the virtual machine
$05
new screen of bytecode for the virtual machine
$ff
end of the answer
5.2 Structure of the modifications of the sources
The operations on the sources make it possible the waiter to modify the values of the RAM
“sources” of the machine virtual, accessible via instruction SRC from the virtual machine.
The structure of the operation on the sources is as follows:
- identifier of the screen: 4 bytes
- then from 1 to 63 bytes containing the values to place in the RAM “sources”, to leave
address 0.
5.3 Structure of the screens of bytecode
Offset
Cut
Label
Description
000
(5)
magic
`amber'
005
(4)
id
identifier of the screen
Page 17
009
(1)
transition
flag of transition (1: immediate)
00a
(4)
size_prog
cut program
00e
(size_prog)
program
code program (the first byte of it
block corresponds to address 17, or 0x11)
(size_prog+14)
(4)
nb_mus
a number of musics
(size_prog+18)
(4)
music1
offset block music 1 (=taille music 0)
…
(size_prog+4.nb_mus+18)
(..)
music0 given music 0 (offset
for the calculation of the blocks of music)
…
(1)
checksum
…
(4)
magic
`mind'
The checksum is calculated so that the sum of all the bytes of the screen makes
255.